MOSFETs fabricated with conventional silicon-on-insulator (SOI) technology include partially depleted MOSFETs and fully depleted MOSFETs. For partially depleted MOSFETs (PDSOI), the silicon overlayer is thicker than the depth of the depletion region such that the depletion region only extends partially through the silicon overlayer. On the other hand fully depleted SOI MOSFETs (FDSOI) have a thin silicon overlayer, such that the depletion zone substantially extends through the entire depth of the silicon overlayer. In conventional SOI MOSFETs (PDSOI and FDSOI) a threshold voltage of the MOSFET is adjusted using halo implants in the channel (near the source and drain), and threshold voltage implants in the channel.
A key setting for an SOI MOSFET is the threshold voltage, which in turn determines the voltage at which a transistor can be switched. Low threshold voltage devices switch faster and they are generally used for high speed circuits, but they have higher static leakage power. High threshold voltage devices have lower static leakage power and they are generally used for low speed circuits. Typically, a range of threshold voltage settings is used in an integrated circuit device depending on the design parameters and desired characteristics for a particular circuit block. It is generally known that variation in threshold voltage from the specification for the device is undesirable. In conventional SOI MOSFETs (both PDSOI and FDSOI), threshold voltage is typically adjusted by incorporating dopants into the transistor channel, either by way of direct channel implantation adjacent the gate oxide or by way of pocket or halo implants adjacent the source and drain. Threshold voltage variation can arise because of random dopant fluctuations in the implanted channel area. The variation problem worsens as critical dimensions shrink because of the greater impact of dopant fluctuations as the affected volume of the channel becomes smaller.